Sundaram S S
Hardware Security & FPGA/SoC engineer focused on protocol-correct RTL, secure Ethernet datapaths, AXI4-Lite/AXI-Stream integration, DMA/interrupt-driven systems, and validation on real Xilinx Zynq/Kria hardware.
Quick Snapshot
FPGA & SOC INTEGRATION
Xilinx Zynq-7000 / Kria (KV260 / KR260)
AXI4-Lite control/status register design
AXI-Stream datapaths for high-throughput data flow
AXI DMA integration (MM2S / S2MM)
SmartConnect / interconnect configuration
Interrupt routing via GIC
VERIFICATION & DEBUG
Simulation-driven RTL validation
UVM-based verification (drivers, monitors, scoreboards, coverage)
AXI protocol assertions and constrained-random stimulus
On-chip debug using Integrated Logic Analyzer (ILA)
HW/SW CO-DESIGN
Bare-metal Embedded C
DMA buffer management and cache coherency handling
Interrupt-driven control flow
UART-based runtime validation and logging
XSA export → Vitis application bring-up
RTL & MICRO-ARCHITECTURE
Synthesizable Verilog / SystemVerilog RTL
FSMs, pipelines, counters, monitors, datapath control
Reset strategy, CDC awareness, timing-closure-driven coding
Protocol-correct streaming logic (ready/valid discipline)
Core Strengths
RTL Design & Verification
Hardware Security & FPGA/SoC engineer focused on protocol-correct RTL, secure Ethernet datapaths, AXI4-Lite/AXI-Stream integration, DMA/interrupt-driven systems, and validation on real Xilinx Zynq/Kria hardware.
FPGA SoC Integration
Hardware Security & FPGA/SoC engineer focused on protocol-correct RTL, secure Ethernet datapaths, AXI4-Lite/AXI-Stream integration, DMA/interrupt-driven systems, and validation on real Xilinx Zynq/Kria hardware.
Embedded C & Networking
Hardware Security & FPGA/SoC engineer focused on protocol-correct RTL, secure Ethernet datapaths, AXI4-Lite/AXI-Stream integration, DMA/interrupt-driven systems, and validation on real Xilinx Zynq/Kria hardware.
EDA Tools & Workflows
Hardware Security & FPGA/SoC engineer focused on protocol-correct RTL, secure Ethernet datapaths, AXI4-Lite/AXI-Stream integration, DMA/interrupt-driven systems, and validation on real Xilinx Zynq/Kria hardware.
