Digital & RTL Design (Frontend VLSI)

Designing synthesizable RTL with clear micro-architecture
FSM-based control, pipelined datapaths, and streaming logic
Reset strategy, CDC awareness, and timing-driven design thinking
Writing RTL that is easy to verify, integrate, and maintain

Target roles:
RTL Design Engineer, Digital Design Engineer, ASIC/FPGA Frontend

FPGA Prototyping & Pre-Silicon Validation

FPGA-based prototyping of SoC and IP designs
Functional and performance validation on real hardware
Debug using on-chip instrumentation (ILA)
Using FPGA results to inform architectural decisions

Target roles:
FPGA Engineer, Pre-Silicon Validation Engineer

Embedded Systems & HW/SW Co-Design

Bare-metal Embedded for SoC control
Register-level hardware interaction
DMA buffer management and interrupt handling
End-to-end system bring-up and debug

Target roles:
Embedded Systems Engineer, Firmware Engineer (Silicon)

Hardware Security-Aware Design

Secure Ethernet datapaths and packet inspection concepts
Hardware-level anomaly indicators
Security-aware register and control plane design
Foundational understanding of attack surfaces in hardware systems

Target roles:
Hardware Security Engineer, Secure SoC Engineer

Verification & Design Validation

Simulation-driven verification mindset
Exposure to UVM methodology (drivers, monitors, coverage)
AXI protocol correctness checking
Hardware validation using ILA and real-system testing

Target roles:
Design Verification Engineer, SoC Validation Engineer