About
I am a hardware-focused engineer specializing in digital RTL design, FPGA prototyping, and hardware security-centric system architecture. My work emphasizes protocol-correct AXI interfaces, timing-clean implementations, and system-level validation on real hardware.
Who I am as an engineer
I am a hardware-focused VLSI / FPGA / SoC engineer specializing in protocol-correct RTL design, AXI-centric system integration, and secure Ethernet datapaths.
My work focuses on building robust, timing-clean, and debuggable hardware systems on Xilinx Zynq and Kria platforms, combining RTL, embedded software, and system-level validation.
I approach design with an industry mindset: correctness first, measurable performance, and validation on real hardware, not simulation alone.
How I work and what I build
I work across the full hardware development lifecycle:
RTL micro-architecture (FSMs, pipelines, AXI-Stream datapaths)
SoC integration (AXI4-Lite control, DMA, interrupts, DDR)
HW/SW co-design (bare-metal C for control and orchestration)
Verification & debug (simulation, UVM exposure, ILA, Wireshark)
I emphasize protocol discipline, timing awareness, and observability, ensuring designs are easy to validate, debug, and scale.
Where I am heading
My long-term interests lie in hardware security and high-performance SoC architectures, particularly:
Secure network-centric FPGA datapaths
Hardware-based anomaly detection and monitoring
Side-channel-resistant micro-architectures
Power- and timing-driven digital design
Post-quantum cryptography (PQC) hardware acceleration
I actively align academic research with practical, deployable hardware systems, aiming to bridge the gap between theory and real-world silicon constraints.