Designed and evaluated a Layer-2 VLAN switching pipeline on Zynq SoC platforms, progressing from network simulation to bare-metal hardware bring-up. The project focused on understanding practical limitations of PS-only Ethernet switching, DMA throughput, PHY control, and board-level constraints on commercial FPGA platforms.

Developed RTL streaming pipelines to compute entropy-related metrics on live packet streams using AXI-Stream, enabling low-latency anomaly indicators directly in hardware. The design emphasizes protocol correctness, throughput safety, and observability.

Designed and validated a bare-metal 17-rule Layer-2 ARP/MAC/STP security engine on Zynq-7000 SoC, progressing from rule specification through live tcpreplay attack injection at 100 kpps. Work spanned DMA ring management (260k BDs), PHY/GEM bring-up, proportional token-bucket rate limiting.

Built a UVM-based verification environment for an AXI master interface, focusing on protocol correctness, constrained-random stimulus, and functional coverage. This project demonstrates verification methodology beyond simulation-only RTL testing.

Explored Network-on-Chip (NoC) architectures for chiplet-based SoCs using graph-theoretic optimization techniques. The work focused on balancing latency, bandwidth, and scalability under physical design constraints.

Designed a custom AXI4-Lite slave IP implementing an 8-bit Linear Feedback Shift Register (LFSR) and integrated it into a Zynq SoC. The IP was controlled and validated via a bare-metal Embedded C application, demonstrating full RTL-to-software integration.

Designed a 12-tap FIR filter and compared its implementation across FPGA and ASIC flows, focusing on power, performance, and area (PPA) trade-offs. This project highlights architectural decision-making across platforms.