Skills
Highlighting key skills in languages, protocols, tools, and system competencies.
RTL Design & Verification
Verilog, SystemVerilog (synthesizable RTL)
Streaming datapaths, FSMs, pipelines, counters/monitors
AXI-Stream correctness (tvalid/tready), backpressure-safe design
CDC awareness, reset strategy, timing closure mindset
Simulation debug: waveforms, assertions/coverage
FPGA SoC & AXI Integration
AXI-Lite control registers, address maps, control/status design
AXI DMA usage patterns, buffer descriptors, interrupt-driven flows
SmartConnect/interconnect, throughput-oriented datapath planning
On-chip debug with ILA, trigger-based capture
Embedded Systems & Networking
Embedded C (bare-metal), interrupt handling, ring buffers
PS GEM Ethernet basics, PHY link/MDIO awareness
VLAN concepts, ARP behavior, packet parsing basics
Wireshark validation for functional + timing behavior
EDA Tools & Platforms
Xilinx Vivado/Vitis flows (build, bitstream, XSA export)
Cadence Virtuoso/Innovus, Synopsys Genus (exposure/workflows)
MATLAB/Simulink modeling for DSP + HDL generation